Comp Arch Cache C

Cache access time is often considered the slowest part of CPU execution.

AAT = Hit Time + Miss Rate * Mem Time (Mem Time includes the Hit time of next level cache)

Extensive efforts are made to speed up this process, including

  1. Build better physical cache to slow down Hit Time and Mem Time.
  2. Modify cache configuration to reduce Miss Rate.

Better cache often requires extensive material science research that would last years and cost much investment. The end product are often of higher build cost. The other approach can often improve the end performance better since

  1. Computer instructions are, afterall, manmade products that there are rules to be followed and therefore rooms to be exploited.
  2. Cache miss and hit are a probability problem. While there is a theoretical optima, there are ways to approximate to get closer to the theoretical optima.

Here, this simulator explore the performance a hierarchical cache of L1, L2 and victim cache with various configuration in associativity, cache size, and collinsion policy on final cache access time.

Git Code and Report.